The present invention is related to operation, use and control of a bus. More particularly, the present invention is related to the operation, use and control of different operating frequencies of a PCI-X bus.
Computer systems may utilize one or more buses as an interconnect transportation mechanism to transfer data between different internal components, such as one or more processors, memory subsystems and input/output (I/O) devices including, for example, keyboards, input mouses, disk controllers, serial and parallel ports to printers, scanners, and display devices. For computer systems using processors such as the 8088, 9086, 80186, i386(trademark) and i486(trademark) microprocessors designed and manufactured by Intel Corporation, such buses have typically been designed as either an Industry Standard Architecture (ISA) bus or an Expanded Industry Standard Architecture (EISA) bus. The ISA bus is a sixteen (16) bit data bus while the EISA bus is thirty-two (32) bits wide. Each of these buses may function at a frequency of eight (8) megahertz. However, the data transfer rates provided by these bus widths and operational frequencies may be limited.
For recent computer systems, such as servers, workstations or personal computers (PCs) using a xe2x80x9cPentium(copyright)xe2x80x9d family of microprocessors (manufactured by Intel Corporation), for example, such buses may be Peripheral Component Interconnect (PCI) buses. The PCI buses are high performance 32 or 64 bit synchronous buses with automatic configurability and multiplexed address, control and data lines as described in the version of xe2x80x9cPCI Local Bus Specification, revision 2.2xe2x80x9d set forth by the PCI Special Interest Group (SIG) on Dec. 18, 1998. The PCI architecture may provide the most common method used to extend computer systems for add-on arrangements (e.g., expansion cards) with new video, networking, or disk memory storage capabilities.
When PCI buses are used as an interconnect transportation mechanism in a host system (e.g., server, workstation or PC), data transfer between a processor, a memory subsystem and I/O devices may be executed at high speed. Bridges (or hubs) may be provided to interface and buffer transfers of data between the processor, the memory subsystem, the I/O devices and the PCI buses. Examples of such bridges may include PCIxe2x80x94PCI bridges as described in detail in the xe2x80x9cPCIxe2x80x94PCI Bridge Architecture Specification, revision 1.1xe2x80x9d set forth by the PCI Special Interest Group (SIG) on Apr. 5, 1995.